View VV6301_9088075.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary release ? mono and colour qsif digital video cmos image sensors cd5301-6301-1: rev 1.0 october 1999 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 1/49 vv5301 & VV6301 commercial in confidence preliminary release the vv5301 and VV6301 are highly integrated digital output imaging devices based on stmicroelectronicss unique cmos sensor technology. both of these sensors require minimal support circuitry and provide an ideal low cost imaging solution. vv5301 (monochrome) and VV6301 (colourised) produce digital video output. the video streams from both devices contain embedded control data that can be used to enable frame grabbing applications. the pixel array of the VV6301 has colour filters forming a bayer colour pattern. this sensor requires software to perform colour processing to allow an image to be displayed on a pc. the sensor can perform automatic black calibration to remove voltage offsets in the video signal path that lead to offsets in the output image. these offsets are removed using 2 digital to analogue convertors (dacs). the automatic black calibration algorithm monitors the average level of the sensor black pixels and adjusts the input level to the 2 dacs to remove the offset. a 2 wire serial interface allows the sensor to be reconfigured if required. functional block diagram sample & hold horizontal shift register photo diode array analog voltage refs. digital control logic sda scl d[7:0] vertical shift register clki clko clock circuit image format a/d convertor sin fst qck key features ? qsif resolution sensor ? automatic exposure/gain control ? multiple digital output formats available ? i2c interface for sensor control ? integrated 8bit adc ? on board voltage regulator ? automatic black calibration ? variable frame rate ? reduced flicker operating modes application areas ? toys ? automotive systems ? intelligent imaging sensors speci?cations maximum pixel resolution 164 x 124 effective image size after colour processing 160 x 120 pixel size 12.0 m m x 12.0 m m array size 1.92mm x 1.44mm exposure control automatic (range 25000:1) analogue gain +18db signal/noise ratio 36db supply voltage 5v dc +/- 5% supply current vv5301-VV6301 2.9ma (standby) 14.6ma (active) operating temperature (ambient) 0 o c - 40 o c (for extended temperature informa- tion please contact stmicroelec- tronics) package type 48bga
vv5301 & VV6301 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 2/49 table of contents 1. introduction ................................................................................................................. ..... 4 1.1 overview .................................................................................................................... ....................... 4 1.2 exposure, clock division and gain control ................................................................................... ... 4 1.3 digital interface ........................................................................................................... ...................... 4 2. operating modes .............................................................................................................. 6 2.1 video timing ................................................................................................................ ..................... 6 2.2 pixel array................................................................................................................. ........................ 6 2.3 system clock generation ..................................................................................................... ............ 9 2.4 calculating sensor framerate ................................................................................................ .......... 9 3. auto black calibration................................................................................................... 11 4. exposure control ........................................................................................................... 12 3. auto black calibration................................................................................................... 11 4. exposure control ........................................................................................................... 12 4.1 calculating exposure period................................................................................................. .......... 12 4.2 automatic exposure control .................................................................................................. ......... 12 4.3 updating exposure, gain and clock division settings ................................................................... 12 4.4 clock control ............................................................................................................... ................... 12 4.5 gain setting ................................................................................................................ .................... 13 5. timed serial interface parameters ............................................................................... 14 5.1 listing and categorizing the parameters..................................................................................... ... 14 5.2 timed parameter update points............................................................................................... ...... 14 6. digital video interface format ...................................................................................... 15 6.1 embedded control data....................................................................................................... ............ 15 6.2 8-wire parallel mode ........................................................................................................ .............. 17 6.3 4-wire parallel mode ........................................................................................................ .............. 17 6.4 video frame composition ..................................................................................................... ......... 18 6.5 qualifying the output data.................................................................................................. ............ 22 7. serial control bus .......................................................................................................... 2 6 7.1 general description ......................................................................................................... ............... 26 7.2 serial communication protocol............................................................................................... ........ 26 7.3 data format ................................................................................................................. ................... 26 7.4 message interpretation ...................................................................................................... ............. 27 7.5 the programmers model ....................................................................................................... ......... 28 7.6 types of messages........................................................................................................... .............. 38 7.7 serial interface timing ..................................................................................................... ............... 40 8. detailed ac/dc specification........................................................................................ 42
vv5301 & VV6301 3/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 8.1 vv5301/VV6301 ac/dc specification........................................................................................... .42 8.2 vv5301/VV6301 power consumption ............................................................................................ 4 2 8.3 digital input pad pull-up and pull-down resistors.......................................................................... 4 2 9. pinout and pin descriptions ......................................................................................... 43 10. vv5301/VV6301 recommended reference design..................................................... 45 11. package details (48 pin bga (vv5301/VV6301)) ......................................................... 46 12. evaluation kits (evks) .................................................................................................. 47 13. ordering details ............................................................................................................ .48
vv5301 & VV6301 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 4/49 1. introduction 1.1 overview vv5301/VV6301 is a sif format cmos image sensor. the vv5301 sensor is a monochrome device and the VV6301 is the colourised variant. important: the sensors output video data stream only contains raw data. a microprocessor and supporting software are required to generate a video waveform that can be displayed on a vdu vv5301/VV6301 have an on-board 8bit adc, this limits the number of components required to form a complete digital imaging system. the vv5301/VV6301 sensor will output an image size of 164 x 124. this is an oversized qsif image. the extra pixels that the form the 2 pixel deep border that surrounds the true qsif image are made available to the external colour processing algorithm. 1.2 exposure, clock division and gain control vv5301/VV6301 have an internal automatic exposure/gain control algorithm. this algorithm can be disabled allowing the user to externally control the exposure. the externally calculated exposure, clock division and gain control settings would then be written to the sensor via the i2c interface. 1.3 digital interface vv5301/VV6301 have a flexible digital interface, the main components of which are listed below: 1. a tri-stateable 8-wire data bus (d[7:0]) for sending both video data and embedded timing references. 2. 4-wire and 8-wire data bus alternatives available. 3. a data quali?cation clock, qck, which can be programmable via the serial interface to behave in a number of different ways (tri-stateable). 4. a line start signal, lst (tri-stateable). 5. a frame start signal, fst (tri-stateable). 6. oeb tri-states all 5 data bus lines, d[4:0], the quali?cation clock, qck and fst. 7. the ability to synchronise the operation of multiple cameras (sensor produces a synchronisation out pulse, sno). 8. a 2-wire serial interface (sda,scl) for controlling and setting up the device. 1.3.1 digital data bus along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within th e video data stream to allow a co-processor to synchronise with video data the camera module is generating section 6.defines the format for the output video data stream. 1.3.2 frame grabber control signals to complement the embedded control sequences the data qualification clock (qck) and the field start signal (fst) signals can be independently set-up as follows: 1. disabled 2. free-running. 3. qualify only the control sequences and the pixel data. 4. qualify the pixel data only mode input clock (mhz) note system clock divisor image size line time ( m s) lines per frame frame rate (fps) qsif - 25 fps 14.318 1 164 x 124 271.502 147 25.06 qcif - 30 fps 17.73 1 164 x 124 227.36 147 29.92
vv5301 & VV6301 5/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 1.3.3 2-wire serial interface the 2-wire serial interface provides complete control over sensor setup and operation. two serial interface broadcast addresses are supported. one allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written to in parallel. section 7. defines the serial interface communications protocol and the register map of all the locations which can be accessed via the serial interface. 1.4 other features 1.4.1 tristating digital outputs the qck, fst and databus[7:0] pins can be tristated. the qck pin can be independently tristated by driving the qcktri pin low. the qck, fst and upper nibble of the databus can also be tristated via a serial register control bit, see register[116] fo r more details. the lower nibble of the databus can also be independently tristated using a different control bit in register[116 ]. 1.4.2 synchronising video timing the video timing logic in vv5301/VV6301 can be synchronised, i.e. reset to the beginning of a timing field, by an external pin, sin. this pin is normally low. to enable the synchronising feature the user must drive the pin high for a number of clock periods, c.10 clki periods, then drive it low again. this synchronisation should only be done every other field as the sensor has a 2 field repeat cycle requirement for the video timing. if the sin pin was asserted every field the exposure controller and application of new external exposure and gain settings would not operate correctly. 1.4.3 pixel hold feature the hpix signal can be used to freeze the internal adc, forcing the sensor to stop converting new pixel values. if the hpix is driven high then the adc will maintain the currently converted pixel value. this feature is intended to function as an external pixel defect correction system, albeit a ver basic example.
vv5301 & VV6301 operating modes preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 6/49 2. operating modes 2.1 video timing the video format mode on power-up is qsif 30fps by default, although a 25fps mode can also be selected, see serial register[17], bit 6. the number of active video lines in each mode is the same (124) for both the qsif modes. the slower frame rate (25 fps) is implemented by simply extending the line period from 203 pixel periods to 301 pixel periods. table 1 details the setup for each of the video timing modes. 2.2 pixel array the physical pixel array is 168 x 124 pixels. the pixel size is 12.0 m m by 12.0 m m. the output video image size is 164 x 124 pixels. the border pixels from the array are used as a shield from edge effects. figure 3 shows how the 164 x 124 is aligned within the bigger 168 x 124 pixel array. image read-out is flexible. by default the sensor read out is configured to be horizontally non-shuffled non-interlaced raster scan. the horizontally shuffled raster scan order differs from a conventional raster in that the pixels of individual rows are re-ordered, with the even pixels within a row read- out first, followed by the odd pixels. this shuffled read-out within a line, groups pixels of the same colour (according to the bayer pattern - figure 1) together, reducing cross talk between the colour channels. the horizontal shuffle option would normally onl y be selected with the colour sensor variant, VV6301. video mode clock (mhz) system clock divisor video data line length field length output mode qsif (30fps) 14.318 1 164 x 124 203 147 4-wire qsif (25fps) 17.73 1 164 x 124 301 147 4-wire table 1 : video timing modes figure 1 : bayer colourisation pattern (VV6301 only) green 1 blue green 2 red odd rows (0,2,4,6,...) even rows (1,3,5,7,...) odd columns (0,2,4,6,...) even columns (1,3,5,7,...)
operating modes vv5301 & VV6301 7/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release rrrrrrgggggg grgrgrgrgrgr where g - green and r - red figure 2 : horizontal shuf?e enabled
vv5301 & VV6301 operating modes preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 8/49 blue green green red blue green green red 164 pixels 124 pixels 4 3 2 1 2 4 3 1 6 5 1,2,3,4,5,6,... ..., 164,165,166,167,168 1,2,3,4,5,6,8,... .120.,121,122,123,124 blue green green red 6 5 8 7 164 163 162 161 166 165 168 167 168pixels blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red the colour dyes included in this diagram are only applicable to VV6301. the monochrome device vv5301 has exactly the same readout structure and array size as VV6301 - but no colourised pixels 120 122 121 119 124 123 figure 3 : image readout order please note the column read out order. if the readout is unshuffled then the readout order is even,odd,even etc. if the readout is shuffled, to avoid colour channel crosstalk, then all the even columns are readout first followed by the odd columns. 3 pixel band 1 pixel band
operating modes vv5301 & VV6301 9/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 2.3 system clock generation vv5301/VV6301 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the clki and clko pins. the device can also be driven directly from an external clock source driving clki. figure 4 : camera clock source for greater flexibility the input frequency can be divided by 1, 2, 4 or 8 to select the pixel clock frequency. two bits in th e clock division register in the serial interface select the input clock frequency divisor. the table below gives the different frame rates that can be selected, when clki = 14.318mhz, for up to 30frames per second, for each divisor. 2.4 calculating sensor framerate the vv5301/VV6301 frame rate depends upon: ? the frequency of the system clock (clki) ? the adc conversion accuracy (8-bit) ? the internal clock divisor selected (1, 2, 4, or 8) ? the output format is a constant 2 user can set their own values for clki and also the clock divisor setting. the frame rate is determined as follows an example is given with a clock input of 14.318mhz, 160 x120 (164 x 124) image format, 8-bit adc conversion rate and a clock divisor of 2. 1. determine clock input (clki) frequency - 14.318mhz 2. pixel period = (divisor x conversion factor x output format factor) / clki clki (mhz) divisor pixel period (us) frame rate comments 14.318 1 1.1175 29.99 default 14.318 2 2.235 15.01 14.318 4 4.47 7.5 14.318 8 8.94 3.75 table 2 : clock division (60hz video mode) x1 c2 c1 r1 32 31 ckin ckout clk vv5301/VV6301 32 31 ckin ckout cmos driver clock source r2 c1=c2=47pf r1=1m w r2=510 w x1= 14.318mhz (up to 30fps) 17.73mhz (up to 25fps) clock division clk clock division vv5301/VV6301
vv5301 & VV6301 operating modes preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 10/49 clock divisor = 1, 2, 4 or 8. conversion factor = 8 for 8-bit adc accuracy output format factor is 2 example: pixel period = (2 x 8 x 2) / 14.318mhz = 2.235 m s 3. line period = (no. of visible pixels + line overhead) x pixel period the number of visible pixels per line is 160. the interline pixel period overhead (including the 4 border pixels that can be enabled to qualify extra video information) is mode dependent, 43 pixel periods for 60hz mode or 141 pixel periods for 50hz mode. example: line period = (160 + 43) x 2.235 m s = 453.705 m s 4. frame period = (no. of visible lines + frame overhead) x line period for the purposes of calculating the effective frame rate the number of active lines is assumed to be fixed at 120. the frame overhead (which includes the 4 border lines that can be enabled to qualify extra video information) has a constant value of 27 line periods. example: frame period = (120 + 27) x 453.705 m s = 66.694ms giving a frame rate = 1 / frame period = 15 frames per second
auto black calibration vv5301 & VV6301 11/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 3. auto black calibration black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal. the vv5/6301 is equipped with an automatic function that continually monitors the output black level and calibrates if it has moved out of rang e. the signal is corrected using two black-cal dacs, b0 and b1, shown below figure 5 : block diagram of black calibration system black calibration can be split into two stages, monitor (1 cycle over 2 lines) and update (3 cycles, each cycle takes 2 lines). during the monitor phase the current black level is compared against two threshold values. if the current value falls outside t he threshold window then an update cycle is triggered. the update cycle can also be triggered by a change in the gain applied to sensor core or via the serial interface. 3.1 monitor procedure the decision on when to re-calibrate the black level is made during the first cycle through the black reference lines. the decision area for the black monitor is by default the last 16 pixels of the middle 128 pixels of the second designated black line, line 2. however if this set of pixels fail to give a good black level then it is possible to use the penultimate group of 16 pixels. the black reference pixels are summed, averaged and then compared with the monitor window. if the average falls outside the window a flag is then set to force a re-calibration of the dac values. 3.2 update the black calibration update sequence requires three phases and is performed over the remaining black lines at the start of the video field, lines 3 to 8. during the first phase initial b0 dac calibration is performed. in the second, the b1 dac is calibra ted within the limitation of its step size. in the final phase the black level is fine tuned by re-calibrating the bo dac.this is due to the b1 dac having a relatively coarse step size when high gain is applied. the two calibration phases for the b0 dac differ in that the first time it is calibrated it is working on common mode data. dur ing the final phase the b0 dac is fine-tuned using black reference pixels. g2:0] data[7:0] s/h amp adclk blk sig 8bit adc b1 dac (8bit) b0 dac (8bit) vsig vref from sensor adsam array to digital logic
vv5301 & VV6301 exposure control preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 12/49 4. exposure control 4.1 calculating exposure period the exposure time, comprising coarse and fine components, for a pixel and the analogue gain are programmable via the serial interface. the coarse exposure value sets the number of complete lines a pixel exposes for, while the fine exposure sets the number of additional pixel clock cycles a pixel integrates for. the sum of the two gives the overall exposure time for the pixel array. exposure time = ((coarse setting x line period) + (fine setting)) x (clki clock period) x clock divider ratio note1 note1: clock divider ratio = 1/(basic clock division * optional pixel clock divisor) 4.2 automatic exposure control with automatic exposure control selected vv5301/VV6301 uses a complex algorithm to automatically set the exposure value for the current scene. when combined with clock control and gain control the vv5301/VV6301 can operate over a very wide range of illumination levels. 4.3 updating exposure, gain and clock division settings although the user can write a new exposure, gain or clock division parameter at any point within the field the sensor will only consume these new external values at a certain point. the exception to this behaviour are when the user has selected immediate update of gain if the user has selected the former then the new gain value will be applied as soon as the serial interface message has completed. the fine and coarse exposure values are always written in a timed manner. there are two update pending flags available to the user (see status0 reg[2] for details) that allows the user to detect when the sensor has consumed one of the timed parameters. in the next section of this document we will detail all the timed parameters and describe when they are updated. it is important to realise that there is a 1 frame latency between a new exposure value being applied to the sensor array and t he results of this new exposure value being read-out. the same latency does not exist for the gain value. to ensure that the effect of the new exposure and gain values are coincident the sensor delays the application of the new gain value by approximately one frame relative to the application of the new exposure value. if the user is using the autoincrement option in the serial interface when writing a new series of exposure/gain and clock divi sion parameters then it is important to ensure that the sensor receives the complete message bunch before updating any of the parameters. it is also important that the timed parameters are updated in the correct order, we will discuss this fully in the next section. if an autoincrement message sequence is in progress but we have reached the point in the field timing where the gain value would normally be updated, we actually inhibit the update. we inhibit the update to ensure that the gain change is not passed to the sensor while a change in the exposure is still pending. 4.4 clock control the system clock can be divided down internally to extend the operating range of vv5301/VV6301 by allowing longer exposure times. the clock divisor options are as follows: if the user increases the clock divisor setting then the effective exposure period is also increased. clock divisor register effective clock division 2b00 1 2b01 2 2b10 4 2b11 8 table 3 : available clock division
exposure control vv5301 & VV6301 13/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 4.5 gain setting an external gain value can be written to the sensor as follows. if the image is to dark and the exposure is already close to its maximum the automatic exposure algorithm will attempt to use extra steps of gain to improve the image brightness. each change applied by the internal algorithm will double the current value. to compensate for this increase in gain the current exposure is set to half of the maximum value. this should ensure that the user will not be aware of a step change in the scene brightness. similarly if the image is too bright and the integration period is short then gain will be reduced by one step (i.e. divide by two). as before, the exposure value is set to half the maximum integration period. the exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image. if the user disables the automatic exposure/gain controller then the extra gain settings detailed in table 4 above are availabl e. gain binary code effective system gain 000 1.000 001 2.000 010 1.333 011 4.000 100 1.143 101 2.667 110 1.600 111 8.000 table 4 : gain settings
vv5301 & VV6301 timed serial interface parameters preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 14/49 5. timed serial interface parameters the previous section, exposure control, introduced the concept of a timed parameter, that is information that is written via the serial interface but will not be used immediately by the sensor, rather there will be a delay before the information is passed to the internal registers (referred to as the working registers) from the serial interface registers (referred to as the shadow registers). it is the contents of the working registers that will determine sensor behaviour. 5.1 listing and categorizing the parameters the timed parameters are split into 2 categories as follows: ? fine and coarse exposure ? gain there is a pending flag for each of the above categories. these flags are stored in status0 register[2] in bits [0] and [2]. if one of the flags is high this indicates that the working register/s controlled by that flag have yet to be updated from the accordi ng shadow register/s. this feedback information could be useful if a user is, for example, attempting to write an external exposur e controller. the status of the pending flags allows accurate timing of the serial interface communications. 5.1.1 fine and coarse exposure the exposure category comprises registers[32,33] and [34,35]. 5.1.2 gain the gain category simply comprises register[36]. 5.2 timed parameter update points the timed parameter categories are updated as follows: note: we refer to odd and even fields in the table below. each field is identical in length but we have to be able to different iate between fields to enable correct updating of register parameters. if a change in exposure and gain are pending at the same time then the exposure value will be updated first followed by the gain. this will ensure image illumination continuity from field to field. timed parameter category updated point ?ne and coarse exposure during the interline period between the last line of the odd ?eld and the ?rst line of the even ?eld. gain during the interline period between line 143 and line 144 in the even ?eld. table 5 : timed parameter update points
digital video interface format vv5301 & VV6301 15/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 6. digital video interface format the video interface consists of a bidirectional, tri-stateable 5-wire data bus. the nibble transmission is synchronised to the rising edge of the system clock. digital video data is 8 bits per sample in vv5301 and VV6301. the data can be transmitted in the following ways: ? a single 8 bit byte over 8 output wires note . ? a series pair of 4-bit nibbles, most significant nibble first, on 4 wires. 6.1 embedded control data to distinguish the control data from the sampled video data all control data is encapsulated in embedded control sequences. these are 6 bytes long and include a combined escape/sync character sequence, 1 control byte (the command byte) and 2 bytes of supplementary data. to minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have been used to allow single bit errors in the embedded control words to be corrected. however, more serious corruption of control words or the corruption of escape/sync characters cannot be tolerated without loss of sync to the data stream. to ensure that a loss of sync is detected a simple set of rules has been devised. the four exceptions to the rules are outlined below: 1. data containing a command word that has two bit errors. 2. data containing two end of line codes that are not separated by a start of line code. 3. data preceding an end of ?eld code before a start of frame code has been received. 4. data containing line that do not have sequential line numbers (excluding the end of ?eld line). if the receiving software or hardware detects one of these violations then it should abandon the current field of video 6.1.1 the combined escape and sync character each embedded control sequence begins with a combined escape and sync character that is made up of three words. the first two of these are ff h ff h - constituting two words that are illegal in normal data. the next word is 00 h - guaranteeing a clear read-out order progressive scan (non-interlaced) form of encoding uniformly quantised, pcm, 8/10 bits per sample correspondence between video signal levels and quantisation levels: the internal10-bit pixel data is clipped to ensure that 0 h and 3ff h (5 wire) or ff h (4/8 wire) values do not occur when pixel data is being output on the data bus. vv5301/VV6301 8-bit data pixel values 1 to 254 black level 16 figure 6 : output modes 4 - wire output mode d 7 ,d 6 ,d 5 ,d 4 d 3 ,d 2 ,d 1 ,d 0 d 3 ,d 2 ,d 1 ,0 2 d 7 ,d 6 ,d 5 ,d 4 8-bit pixel data 8- wire output mode d 7 ,d 6 ,d 5 ,d 4 ,d 3 ,d 2 ,d 1 ,d 0 d 7 ,d 6 ,d 5 ......... ....d 2 ,d 1 ,d 0
vv5301 & VV6301 digital video interface format preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 16/49 signal transition that allows a video processor to determine the position of the word boundaries in the serial stream of nibble s. combined escape and sync characters are always followed by a command byte - making up the four byte minimum embedded control sequence. 6.1.2 the command word the byte that follows the combined escape/sync characters defines the type of embedded control data. three of the 8 bits are used to carry the control information, four are parity bits that allow the video processor to detect and correct a certain le vel of errors in the transmission of the command words, the remaining bit is always set to 1 to ensure that the command word never has the value 00 h . the coding scheme used allows the correction of single bit errors (in the 8-bit sequence) and the detection of 2 bit errors.the even parity bits are based on the following relationships: 1. an even number of ones in the 4-bit sequence (c 2 , c 1 , c 0 and p 0 ). 2. an even number of ones in the 3-bit sequence (c 2 , c 1 , p 1 ). 3. an even number of ones in the 3-bit sequence (c 2 , c 0 , p 2 ). 4. an even number of ones in the 3-bit sequence (c 1 , c 0 , p 3 ). table 7 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors. line code nibble x h (1 c 2 c 1 c 0 ) nibble y h (p 3 p 2 p 1 p 0 ) end of line 1000 2 (8 h ) 0000 2 (0 h ) blank line (bl) 1001 2 (9 h ) 1101 2 (d h ) black line (bk) 1010 2 (a h ) 1011 2 (b h ) visible line (vl) 1011 2 (b h ) 0110 2 (6 h ) start of field (sof) 1100 2 (c h ) 0111 2 (7 h ) end of field (eof) 1101 2 (d h ) 1010 2 (a h ) table 6 : embedded line codes (for 4 wire output mode) parity checks comment p 3 p 2 p 1 p 0 4444 code word un-corrupted 4448 p 0 corrupted, line code ok 4484 p 1 corrupted, line code ok 4844 p 2 corrupted, line code ok 8444 p 3 corrupted, line code ok 8848 c 0 corrupted, invert sense of c 0 8488 c 1 corrupted, invert sense of c 1 4888 c 2 corrupted, invert sense of c 2 all other codes 2-bit error in code word. table 7 : parity checking
digital video interface format vv5301 & VV6301 17/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 6.2 8-wire parallel mode if this output mode is selected then the 8-bit pixel data is output on pins data[7:0]. the data is valid on the falling edge of the pixel qualification clock, qck. 6.3 4-wire parallel mode if the 4-wire parallel mode is selected then a pixel value is output over 2, 4-wire nibbles transmitted over pins data[7:4]. a falling edge on qck will sample a data nibble.
vv5301 & VV6301 digital video interface format preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 18/49 6.4 video frame composition each frame of video sequence comprises 2 fields. each field of data is constructed of the following sequence of data lines. 1. a start of ?eld line 2. a number of black lines 3. a number of blank (or dark) lines 4. a number active video lines 5. an end of ?eld line 6. a number of blank or black lines each line of data starts with an embedded control sequence that identifies the line type (as outlined in). the control sequence is then followed by two bytes that contain a coded line number. the line number sequences starts with the start-of-frame line at 00 h and increments one per line up until the end-of-frame line. each line is terminated with an end-of-line embedded control sequence. the line start embedded sequences must be used to recognise visible video lines as a number of null bytes may be inserted between successive data lines. there are two figures (figure 7 - figure 8) on the following pages that show line type field construction. 6.4.1 blank lines in addition to padding between data lines, actual blank data lines may appear in the positions indicated above. these lines begin video format qsif extra black lines on off 1st field start of field line 1 1 black lines 8 2 blanking lines 2 8 active video lines 124 124 blanking lines 10 10 end of field line 1 1 blanking lines 1 1 total 147 147 2nd field start of field line 1 1 black lines 8 2 blanking lines 2 8 active video lines 124 124 blanking lines 10 10 end of field line 1 1 blanking lines 1 1 total 147 147 table 8 : field and frame composition
digital video interface format vv5301 & VV6301 19/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release with start-of-blank-line embedded control sequences and are constructed identically to active video lines except that they will contain only blank bytes, 07 h , (expressed as 01c h in 10bit form). 6.4.2 black line timing the black lines (which are used for black calibration) are identical in structure to valid video lines except that they begin w ith a start-of-black line code and contain information from the sensor black lines. the user can opt to enable extra black lines up to a maximum of 8. the black calibration algorithm always has access to the data contained within these lines whether they are externally enabled or not.
vv5301 & VV6301 digital video interface format preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 20/49 figure 7 : field and frame formats - extra black lines off frame = 294 lines 2 black lines start of 1st field line end of 1st field line blanking lines 124 visible lines blanking line 1st field = 147 lines 1 0 2 3 9 10 11 135 145 146 blanking lines 134 144 start of 1st field line end of 1st field line 124 visible lines blanking line 0 11 135 145 146 blanking lines 134 144 2nd field = 147 lines start of 1st field line 0 end of 1st field line blanking line 145 146 4 2 black lines blanking lines 1 2 3 9 10 4
digital video interface format vv5301 & VV6301 21/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release figure 8 : field and frame formats - extra black lines on frame = 294 lines 8 black lines start of 1st field line end of 1st field line blanking lines 124 visible lines blanking line 1st field = 147 lines 1 0 2 3 9 10 11 135 145 146 8 blanking lines 134 144 8 black lines start of 1st field line end of 1st field line blanking lines 124 visible lines blanking line 1 0 2 3 9 10 11 135 145 146 8 blanking lines 134 144 2nd field = 147 lines start of 1st field line 0 end of 1st field line blanking line 145 146
vv5301 & VV6301 digital video interface format preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 22/49 6.5 qualifying the output data data is output from vv5301/VV6301 in a continuous stream. by utilizing signals, like fst, and key events, like the start of a line or the end of line, the user can sample and display the image data. qck is used to sample the data, as described in the previous section. different periods of the frame can be qualified by qck. the options, which are selected via setup register4 in the serial interface, are as follows: 1. qck disabled, no data quali?ed (default) 2. qck free running, all data quali?ed 3. qck quali?es image data only, to include data on black lines currently enabled 4. qck quali?es embedded control sequences as well as image data. the status line data is also quali?ed with this option. 6.5.3 frame start signal, fst there are 3 modes of operation for the fst pin programmable via the serial interface: 1. fst disabled, (default). 2. fst enabled, quali?es 3. shutter/electronic flash synchronisation signal - fst rises a the start of the video data in the ?rst black/blank line after the eof line and falls at the end of data in the sof line. the fst output is tri-stated either when oeb is driven high or via the appropriate control bit in the serial interface, (see data_format register[22]).
digital video interface format vv5301 & VV6301 23/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release end of active video (eav) start of active video (sav) pixel data figure 9 : quali?cation of output data (border rows and columns enabled). video data f h line format 4-wire nibble output mode - d[3:0] d 1 d 0 f h f h f h p m p l p m p l p m p l p m p l crystal clock or external clock applied to cki p m = pixel value - most significant nibble, p l = pixel value - least significant nibble, p = 8-bit pixel value quali?cation clock, qck (i) free running (ii) control sequences and pixel data (iii) pixel data only
vv5301 & VV6301 digital video interface format preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 24/49 figure 10 : frame/field level timings for fst and qck. start of field black lines blanking lines visible lines end of field blanking lines blanking lines start of field 2nd field 1 frame start of field black lines blanking lines visible lines end of field blanking lines 1st field frame/field format: qck: (iii) data only (ii) control plus data (i) free running (i) fst (i) sno
digital video interface format vv5301 & VV6301 25/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release figure 11 : line level timings for fst. video data start of active video (sav) eav inter-line period (databus = f h ) end of active video (eav) fst pin: (ii) synchronisation output - sno (i) frame start pulse - qualifies status line information end of active video (eav) 6 pixels 168pixels 6 pixels 1 line video data
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 26/49 7. serial control bus 7.1 general description writing configuration information to the video sensor and reading both sensor status and configuration information back from the sensor is performed via the 2-wire serial interface. communication using the serial bus centres around a number of registers internal to the video sensor. these registers store sensor status, set-up, exposure and system information. most of the registers are read/write allowing the receiving equipment to change their contents. others (such as the chip id) are read only. the main features of the serial interface include: ? broad-cast address to ease setting up multiple camera configurations. ? variable length read/write messages. ? indexed addressing of information source or destination within the sensor. ? automatic update of the index after a read or write message. ? message abort with negative acknowledge from the master. ? byte oriented messages. the contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line. 7.2 serial communication protocol the co- processor or host must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.the communication from host to camera takes the form of 8-bit data with a maximum serial clock video processor frequency of up to 100 khz. since the serial clock is generated by the bus master it determines the data transfer rate. data transfer protocol on the bus is illustrated in figure 12. 7.3 data format information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. the internal data is produced by sampling sda at a rising edge of scl . the external data must be stable during the high period of scl . the exceptions to this are start (s) or stop (p) conditions when sda falls or rises respectively, while scl is high. a message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (sr) followed by another message. the first byte contains the device address byte which includes the data direction read, (r) , ~write , (~w), bit. the lsb of the address byte indicates the direction of the message. if the lsb is set high then the master will read data from the slave and if the lsb is reset low then the master will write data to the slave. after the r, ~w bit is sampled, the data direction cannot be changed, until the next address byte with a new r, ~w bit is received. 12 7 8 a start condition stop condition sda scl acknowledge p s 3 4 56 address or data byte msb lsb figure 12 : serial interface data transfer protocol
serial control bus vv5301 & VV6301 27/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release the byte following the address byte contains the address of the first data byte (also referred to as the index ). the serial interface can address up to 128, byte registers. if the msb of the second byte is set the automatic increment feature of the address index is selected. 7.4 message interpretation all serial interface communications with the sensor must begin with a start condition. if the start condition is followed by a valid address byte then further communications can take place. the sensor will acknowledge the receipt of a valid address by driving the sda wire low. the state of the read/~write bit (lsb of the address byte) is stored and the next byte of data, sampled from sda, can be interpreted. during a write sequence the second byte received is an address index and is used to point to one of the internal registers. the msbit of the following byte is the index auto increment flag. if this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. the master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start , (sr) . if the auto increment feature is used the master does not have to send indexes to accompany the data bytes. as data is received by the slave it is written bit by bit to a serial/parallel register. after each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. during a read message, the current index is read out in the byte following the device address byte. the next byte read from the slave device are the contents of the register addressed by the current index. the contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. at the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. although vv5301/VV6301 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. at the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last location read from or written to. a subsequent read will use this index to begin retrieving data from the internal registers. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. 0 0 1 0 0 0 0 figure 13 : vv5301/VV6301s serial interface address r/w s address[7:1] r / w bit a data[7:0] a sensor acknowledges valid address acknowledge from slave index[6:0] inc p a a data[7:0] [0] address auto increment index bit figure 14 : serial interface data format
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 28/49 7.5 the programmers model there are 128, 8-bit registers within the camera, accessible by the user via the serial interface. they are grouped according t o function with each group occupying a 16-byte page of the location address space. there may be up to eight such groups, although this scheme is purely a conceptual feature and not related to the actual hardware implementation, the primary categories are given below: ? status registers (read only). ? setup registers with bit significant functions. ? exposure parameters that influence output image brightness. ? system functions and analog test bit significant registers. any internal register that can be written to can also be read from. there are a number of read only registers that contain devi ce status information, (e.g. design revision details). names that end with h or l denote the most or least significant part of the internal register. note that unused locations in th e h byte are packed with zeroes. stmicroelectronics sensors that include a 2-wire serial interface are designed with a common address space. if a register parameter is unused in a design, but has been allocated an address in the generic design model, the location is referred to as reserved . if the user attempts to read from any of these reserved or unused locations a default byte will be read back. in vv5301/VV6301 this data is 12 h . a write instruction to a reserved (but unused) location is illegal and would not be successful as the device would not allocate an internal register to the data word contained in the instruction. a detailed description of each register follows. the address indexes are shown as decimal numbers in brackets [....] and are expressed in decimal and hexadecimal respectively. serial register map for vv5301/VV6301 index 10 index 16 name length r/w default comments status registers - [0-15] 0 0 devh 8 ro 1100 0000 2 reserved 1 1 devl 8 ro 0001 0010 2 2 2 status0 8 ro 0000 1000 2 system status information 3 3 unused - 4-6 4-6 unused 8 ro 7 7 frame_av 8 ro average value of pixels in a frame. 8-11 8-b unused 8 ro 12-15 c-f unused - setup registers - [16-31] 16 10 setup0 8 r/w (27 h ) con?gure the digital logic 17 11 setup1 8 r/w (70 h ) con?gure the digital logic 18 12 setup2 8 r/w (1f h ) pixel counter reset value 19 13 setup3 8 r/w (0f h ) exposure control modes 20 14 setup4 8 r/w (00 h ) fst/qck options 21-31 15 unused - exposure registers - [32-47] 32 20 unused - 33 21 ?ne 8 r/w 00 h fine exposure initially zero 34 22 unused - 35 23 coarse 8 r/w 70 h coarse exposure 36 24 gain 8 r/w 00 h gain value
serial control bus vv5301 & VV6301 29/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release a detailed description of each register follows. the address indexes are shown as binary in brackets. 7.5.1 status registers - [0 - 15], [0-f] [0-1], [0-1] -[0-1], [0-1] - deviceh and devicel these registers provide read only information that identifies the sensor type that has been coded as a 12bit number and a 4bit mask set revision identifier. the initial mask revision identifier is 0 i.e. 0000 2 . as the mask set is upgraded the revision identifier will increase, i.e. the second mask set will be 0001 2 and so on. the device identification number for vvl301 is 301 i.e. 0001 0010 1101 2 . 37 25 clk_div 8 r/w 00 h clock division 38 26 gn_lim 8 r/w 07 h maximum allowable gain 39 27 tl 8 r/w 55 h lower exposure control threshold. 40 28 tc 8 r/w 64 h centre exposure control threshold. 41 29 th 8 r/w 73 h upper exposure control threshold. 42-47 2a-2f unused - colour registers - [48-79] 48-79 30-4f reserved video timing registers - [80-103] 80-103 50-67 reserved text overlay registers - [104-107] 104-107 68-6b reserved serial interface autoload registers - [108-111] 108-111 6c-6f reserved system registers - [112-127] 112 70 bdac 8 r/w black calibration setup 113 71 b0 8 ro manual override of black calibration dac register, b0 114 72 b1 8 ro manual override of black calibration dac register, b0 115 73 unused 116 74 tms 8 r/w digital comparator threshold 117 75 unused 118 76 cr0 8 r/w 119 77 cr1 8 r/w 120 78 reserved 120-127 79-7f unused bit function default comment 7:4 device type identifier 1101 2 least significant 4bits of 12bit code identifying the chip type. 3:0 mask set revision identifier 0000 2 table 9 : [0], [0] - devicel serial register map for vv5301/VV6301 index 10 index 16 name length r/w default comments
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 30/49 [2] ,[2] - status0 [7], [7] - [12-15], [e-f] - unused 7.5.2 setup registers - [16 - 31] ,[10-1f] [16], [10] - setup 0 setup 0 register controls some fundamental exposure and output format parameters. defaults are shown in bold type. [17], [11] - setup1 setup 1 register controls registers that are less likely to be modified on a regular basis. the user should note that the borde r pixels/lines can be disabled/enabled independently from the enabling/disabling of the custom analogue horizontal shift register . bits function default comment 7:0 device type identifier 0001_0010 2 most significant 8bits of 12bit code identifying the chip type. table 10 : [1], [1] - deviceh bit function default comment 0 exposure value update pending 0 new exposure setting sent but not yet consumed by the exposure controller 1 unused 0 2 gain value update pending 0 new gain value sent but not yet consumed by the exposure controller 7:4 unused 0 table 11 : [2], [2] - status0 bit function default comment 0 automatic exposure control. off/ on 1 enables or disables automatic exposure control. current exposure value is frozen when disabled. 1 unused 1 2 automatic gain control. off/ on 1 enables or disables automatic gain control. current gain value is frozen when disabled. 4:3 unused 00 2 5 data format select. 1 0 - 8 wire parallel output 1 - 4 wire parallel output 7:6 unused 00 2 table 12 : [16], [10] - setup0 bit function default comment 0 enable additional black lines (3-8) off/ on 0 if enabled extra black lines are visible at device output 1 unused 1 2 enable horizontal shuffle mode. off /on 0 the contents of the horizontal shift register are shuffled so that all the even columns then all the odd columns are read out. table 13 : [17], [11] - setup1
serial control bus vv5301 & VV6301 31/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release [19], [13] - setup3 [20], [14] - setup4 the data output on the serial wire or the 4/8 wire busses can be qualified by an internally generated clock signal, qck. the qck function is assigned a dedicated pin, however the fst pin can also output qck data, if reconfigured. by default, qck is disabled. the qck can free run, qualify the embedded coding sequences and the visible data or the visible data only. fst can also be enabled or disabled, default, or alternatively the fst pin can output a timing signal to synchronise several vv5301/VV6301 sensors or finally the fst pin can output the state of the custom analogue block successive approximation adc output comparator 5:3 unused 110 2 6 50hz timing/ 60hz timing 1 the sensor will produce field rates either suited to 50hz or 60hz (default) operating environments. 7 unused 0 bit function default comment 4:0 unused 6:5 exposure step size 01 selects exposure step size. 1/8 for fast but jerky convergence to 1/64 for slow but smooth convergence. default 1/16. see table 15 for details 7 unused 0 table 14 : [19], [13] - setup3 bit 6 bit 5 step size comment 0 0 1/8 0 1 1/16 default 1 0 1/32 1 1 1/64 table 15 : exposure step size options bit function default comment 1:0 fst/qck pin modes 00 see table 17 below for details 3:2 qck modes 00 see table 18 below for details 5:4 unused 7:6 fst modes 00 see table 19 below for details table 16 : [20], [14] - fg_modes fg_mode[1:0] fst pin qck pin 0 0 fst qck table 17 : fst/qck pin selection bit function default comment table 13 : [17], [11] - setup1
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 32/49 note: the fst pin will always output the free running version of qck (either inverted or normal) . [21-31], [15-1f] - unused 7.5.3 exposure control registers [32 - 47], [20-2f] there is a set of parameters that control the time that the sensor pixels are exposed. the parameters are as follows: fine and coarse exposure time, clock division control and finally gain control. the latter parameter does not affect the integration per iod rather it amplifies the video signal at the output stage of the sensor core. an internal automatic algorithm will, if enabled, continually monitor the pixel output and then, if required, use this data to correct the current exposure. manually changing the divisor applied to the incoming crystal clock can alter the effective integration of the sensor. by slowing the internal clock down the integration period can be increased, i.e. halving the pixel clock frequency will double the integration period. if the user wishes to use the automatic exposure algorithm, the automatic exposure control (controlling fine and coarse exposure) must be enabled. additional gain control is optional. it is also possible to change the gain manually via the serial interface even if the exposure is adjusted automatically. if a user wishes to write an external value to one of the automatic exposure algorithm registers then it is advised that the automatic control for that register be disabled prior to using the serial interface to write the external value. note: the external exposure (coarse, fine or gain) values do not take effect immediately. data from the serial interface is read by the exposure algorithm at the start of a video frame. if the user reads an exposure value via the serial interface then the val ue reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all th e data written to the sensor. between writing the exposure data and the point at which the data is consumed by the exposure algorithm, bit 0 of the status register is set. the gain value is updated a frame later than the coarse and fine exposure parameters. the gain is applied directly 0 1 fst qck 1 0 qck note qck 1 1 invert qck note qck fg_mode[3:2] qck state 0 0 off 0 1 free running 1 0 valid during data and control period of line 1 1 valid only during data period of line table 18 : qck modes fg_mode[7:6]] fst pin 0 0 off 0 1 normal behaviour, fst will qualify the visible pixels in the status line 1 0 synchronisation out pulse, sno 1 1 output adc comparator output, cpo table 19 : fst modes fg_mode[1:0] fst pin qck pin table 17 : fst/qck pin selection
serial control bus vv5301 & VV6301 33/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release at the video output stage and does not require the long set up time of the coarse and fine exposure settings. the automatic exposure algorithm uses a set of exposure threshold settings. these thresholds may also be modified by the user to alter the algorithms performance. the exposure algorithm uses these thresholds in a histogram. the three thresholds divide the histogram into 4 regions, very overexposed, overexposed, underexposed and very underexposed. the pixel data received from the sensor core is compared against the thresholds to determine the accuracy of the current exposure setting. a series of flags are set to describe the outcome of the histogram comparison and the new exposure setting can then be derived. each exposure parameter is subject to a maximum setting. the fine exposure setting can be clamped to a fixed value regardless of the decision made by the automatic algorithm. the clamping will occur if the coarse exposure setting exceeds a predetermined value and the clamping has been enabled via the serial interface. all 8 binary codes can be written to the core via the serial interface. only the 4 thermometer codes 000,001,011 and 111 are selected by the automatic exposure algorithm. the 4 other codes are however still valid and will be evaluated as detailed in th e table below. it is clear, from the non-linear relationship between the binary code and the actual gain applied at the analogue output stage, that care should be taken when using non thermometer code gain settings. if the user writes a gain code of 110 (real gain = 1.600) and then enables automatic gain control and the controller then decided to reduce the gain, the new gain value would be 011 (real gain = 4.000) i.e. the effective applied gain at the analogue output stage has actually been increased . care must be taken when writing manual gain values. the effective system gain for a given binary gain code is as follows: bit function default comment 7:0 fine exposure value 0000_0000 2 (00 h ) maximum fine (50hz mode) = ff h maximum fine (60hz mode) = a8 h table 20 : [33], [21] - fine exposure value bit function default comment 7:0 coarse exposure value 0111_0000 2 (70 h ) maximum coarse (50hz and 60hz modes) = 91 h table 21 : [34], [22] - coarse exposure value bit function default comment 2:0 gain value 0 8 possible gain states can be written via the serial interface table 22 : [36], [24] - gain value vv5301/6301 gain binary code effective system gain 000 1.000 001 2.000 010 1.333 011 4.000 100 1.143 table 23 : system gain
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 34/49 the undivided input crystal clock is used by the clock generator circuitry, elements of the serial interface and a small number of other registers in the design. the remaining digital logic and the analogue circuitry, use internally generated clocks, namely the pixel clock and the faster adc clocks. these clocks are all slower versions of the crystal clock. the adc clocks may be up to half the crystal frequency, but can be further divided by factors of 2, 4 or 8. the pixel clock is lower frequency than the adc cloc k. 101 2.667 110 1.600 111 8.000 bit function default comment 1:0 clock divisor value 0 pixel clock = crystal clock ? 2 n+1 table 24 : [37], [25] - clock divisor value bit function default comment 2:0 gain limit 7 the programmed gain cannot be greater than this value table 25 : [38], [26] - gain limit bit function default comment 7:0 exposure lower threshold 85 table 26 : [39], [27] - exposure lower threshold bit function default comment 7:0 exposure centre threshold 100 table 27 : [40], [28] - exposure centre threshold bit function default comment 7:0 exposure higher threshold 115 table 28 : [41], [29] - exposure higher threshold vv5301/6301 gain binary code effective system gain table 23 : system gain
serial control bus vv5301 & VV6301 35/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release [41-47], [29-2f] - unused [48-111], [30-6f] - reserved 7.5.4 system registers [112-127], [70-7f] [112], [70] - black calibration setup register the sensor contains an automatic function to help maintain an ideal black level for the video signal. the centre 128 pixels, fr om the designated black lines are summed, averaged and then compared with a reference, to determine if the black level has to be adjusted. if an adjustment is required then the values of the 2 dac registers, b0 and b1 - addresses [113-114], [71-72] , can be altered to remove any offset in the video black level. it is strongly recommended that the user select 2b01 for bits[1:0] of register[112], [70]. this will ensure that the black calibration algorithm will run each field. the monitor window size is programmable. if bit 4 of the register above is set then bits[3:2] will determine the size of the monitor window otherwise the current gain setting will fix the monitor window width. there are two dac value adjustment phases during black calibration. the first is a successive approximation technique to establish an approximate value for the dac register. this estimate is then improved by a linear tracking routine. the latter will change the dac register setting if the current pixel average is outwith the black calibration target window. the target window can also be altered via the serial interface. it will only be possible to read back the values of the dac registers, as set by the automatic black cal algorithm, with the vv5301/ VV6301 sensors. bit function default comment 1:0 black calibration trigger select 101 00 - never bcal 01 - always bcal 10 - bcal if failed monitor 11 - bcal if gain has changed 3:2 black calibration monitor window select (pixel average comparison range) 00 00 - 14.00 to 17.9 9 01 - 13.00 to 18.99 10 - 12.00 to 19.99 11 - 11.00 to 20.99 4 monitor window size set by serial interface. yes/ no 0 if enabled the monitor window size is set directly by the user via the serial interface 5 narrow bcal target window yes/ no 0 if enabled the bcal test target window can be narrowed to force pixel black level closer to the ideal 16.00 value. 6 external black calibration dac register values yes/ no 0 if enabled the dac values used by the analogue sensor core 7 unused 0 table 29 : [112], [70] - black calibration window parameters
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 36/49 [116], [74] - system test the sensor can operate in several different test modes. these test modes detect faults in the sensor pixel array and the supporting analogue circuitry. only one test mode should be enabled at any time. [118-119], [76-77] - analogue control registers there are 2 registers used to configure the custom analogue section of the sensor. bit function default comment 7:0 bcal0 80h this register is read only table 30 : [113], [71] - black calibration dac b0 bit function default comment 7:0 bcal1 80h this register is read only table 31 : [114], [72] - black calibration dac b0 bit function default comment 0 reserved 0 1 tristate digital outputs yes/ no 0 if enabled the upper nibble of the data bus, fst & qck will be tristated. 2 reserved 0 3 tristate digital outputs yes/ no 0 if enabled the lower nibble of the data bus will be tristated. 6:4 reserved 7 unused table 32 : [116] ,[74] - system test bit function default comment 0 enable bit line clamp off/ on 0 1 inhibit horizontal shift register off/ on 0 2 enable anti-blooming protection off/ on 0 3 inhibit osa fast reset off/ on 0 4 external bit line white reference off/ on 0 5 inhibit array read during blank lines off/ on 0 disable additional mfi and bloop signals table 33 : [118], [76] - analogue control register 0
serial control bus vv5301 & VV6301 37/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 6 unused 0 7 rst/mrst clock select 0 0 - adck0 1 - adck1 bit function default comment 0 enable mag_b0 off /on 0 double magnitude of b0 dac current 1 new pxrdb scheme off /on 0 2 b1 offset dac high gain select low (x1) /high (x2) 0 b1_hg 3 stand-by off /on 0 powers down all analogue circuitry and the majority of the digital logic 4 unused 0 7:5 rst/mrst phase select 000 the rst/mrst timing signals can be delayed by up to 7 adck periods prior to transfer to the analogue circuits. 000 - no delay 001 - 1 adck period delay 010 - 2 adck period delay 011 - 3 adck period delay 100 - 4 adck period delay 101 - 5 adck period delay 110 - 6 adck period delay 111 - 7 adck period delay table 34 : [119] ,[77] - analogue control register1 bit function default comment table 33 : [118], [76] - analogue control register 0
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 38/49 7.6 types of messages this section gives guidelines on the basic operations to read data from and write data to the serial interface. the serial interface supports variable length messages. a message may contain no data bytes, one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. ? write no data byte, only sets the index for a subsequent read message. ? single location data write or read for monitoring (real time control) ? multiple location read or write for fast information transfers. examples of these operations are given below. a full description of the internal registers is given in the previous section. fo r all examples the slave address used is 32 10 for writing and 33 10 for reading. the write address includes the read/write bit (the lsb) set to zero while this bit is set in the read address. 7.6.1 single location, single data write. when a random value is written to the sensor, the message will look like this: in this example, the fineh exposure register (index = 32 10 ) is set to 85 10 . the r/w bit is set to zero for writing and the inc bit (msbit of the index byte) is set to zero to disable automatic increment of the index after writing the value. the address index is preserved and may be used by a subsequent read. the write message is terminated with a stop condition from the master. 7.6.2 single location, single data read. a read message always contains the index used to get the first byte. this example assumes that a write message has already taken place and the residual index value is 32 10 . a value of 85 10 is read from the fineh exposure register. note that the read message is terminated with a negative acknowledge ( a) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. 7.6.3 no data write followed by same location read. when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be writte n first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages, i.e. no stop condition is asserted. in figure 15 : single location, single write. s 32 10 a0 32 10 a85 10 a p start device ack address index data stop inc figure 16 : single location, single read. s 33 10 a0 32 10 a85 10 a p start device ack address index data stop
serial control bus vv5301 & VV6301 39/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release this example, the gain value (index = 36 10 ) is read as 15 10 : as mentioned in the previous example, the read message is terminated with a negative acknowledge ( a) from the master. 7.6.4 same location multiple data write. it may be desirable to write a succession of data to a common location. this is useful when the status of a bit must be toggled . 7.6.5 same location multiple data read when an exposure related value ( fine h, finel, coarseh, coarse l , gain or clk_div ) is written, it takes effect on the output at the beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure parameters). to signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written and is reset at the start of the next frame. this flag appears in status0 register and may be monitored by the bus master. to speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master acknowledges each byte read. in the below example, a fineh exposure value of 0 is written, the status register is addressed (no data byte) and then constantly read until the master terminates the read message. figure 17 : no data write followed by same location read. s a sr a a a p 33 10 36 10 33 10 36 10 15 10 a 0 0 no data write read index and data sa a a 32 10 21 10 4 10 0 10 a 0 write to pin_mapping figure 18 : same location multiple data write. 4 10 p toggle control bit sa 0 10 a a a 32 10 33 10 32 10 0 10 a 0 sr a a a a 33 10 0 10 1 10 1 10 1 10 a 0 sr write ?nel with zero address the status0 register a 1 10 0 10 a read continuously... ...until ?ag reset p figure 19 : same location multiple data read.
vv5301 & VV6301 serial control bus preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 40/49 7.6.6 multiple location write if the automatic increment bit is set (msb of the index byte), then it is possible to write data bytes to consecutive adjacent internal registers, (i.e. 23,24,25,26 etc), without having to send explicit indexes prior to sending each data byte. an auto-increment write to the exposure registers with their default values is shown in the following example, where we write 17 10 to the pin_mapping register[21] and 193 10 to the data format register[22]. . 7.6.7 multiple location read in the same manner, multiple locations can be read with a single read message. in this example the index is written first, to ensure the exposure related registers are addressed and then they are read. note that the user will get the base index, in this case 32 10 , read back twice before the first data byte is read back. the user must therefore always request an extra byte of data to be read back. note that a stop condition is not required after the final negative acknowledge from the master, the sensor will terminate the communication upon receipt of the negative acknowledge from the master. 7.7 serial interface timing parameter symbol min. max. unit scl clock frequency fscl 0 100 khz bus free time between a stop and a start tbuf 2 - us hold time for a repeated start thd;sta 80 - ns low period of scl tlow 320 - ns high period of scl thigh 160 - ns set-up time for a repeated start tsu;sta 80 - ns data hold time thd;dat 0 - ns data set-up time tsu;dat 0 - ns table 35 : serial interface timing characteristics sa 17 10 a aa 32 10 21 10 193 10 1 incremental write p figure 20 : multiple location write. incremental read sa a 32 10 32 10 1 sr 33 10 aa 32 10 1 32 10 a ap ?neh ?nel coarseh coarsel gain a a a a no data write incremental read figure 21 : multiple location read.
serial control bus vv5301 & VV6301 41/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release rise time of scl, sda tr - 300 ns fall time of scl, sda tf - 300 ns set-up time for a stop tsu;sto 80 - ns capacitive load of each bus line (scl, sda) cb - 200 pf parameter symbol min. max. unit table 35 : serial interface timing characteristics sda scl thd;sta tr thigh tf tsu;dat thd;dat tsu;sta tsu;sto ... ... thd;sta tlow tbuf stop start stop start all values referred to the minimum input level (high) = 3.5v, and maximum input level (low) = 1.5v figure 22 : serial interface timing characteristics
vv5301 & VV6301 detailed ac/dc specification preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 42/49 8. detailed ac/dc speci?cation 8.1 vv5301/VV6301 ac/dc speci?cation table 36 : vv5301/VV6301 ac/dc speci?cation 8.2 vv5301/VV6301 power consumption table 37 : vv5301/VV6301 current consumption in different modes 8.3 digital input pad pull-up and pull-down resistors table 38 : vv5301/ 6301 pull up/pull down resistor speci?cation image format 160 x 120 pixels (qsif) image size output 164 x 124 pixels pixel size 12.5 x 12.5 m m array format sif exposure control up to 44000:1 sensor signal / noise ratio 36db supply voltage 5.0v +/-10% package type 48bga operating temp. range 0 o c - 40 o c logic 0 input 0.2 x vdd max logic 1 input 0.8 x vdd min serial interface frequency range 0-100khz low power mode current consumption 4.6ma normal operating mode current consumption 15.1ma pad type pads typical resistance library pulldown d[7:0],hpix,sin tba library pullup scl, sda, ce, qcktri tba
pinout and pin descriptions vv5301 & VV6301 43/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 9. pinout and pin descriptions bga pin name type description power supplies c5 avss gnd analogue ground a7 avdd pwr analogue power d7 dvdd pwr digital power d5 vdd pwr power g7 vdd pwr power f6 vss gnd ground g2 vss gnd ground f3 vdd pwr power e1 vss gnd ground e2 dvss gnd ground analogue outputs b4 vrt ia pixel reset voltage a5 vcds ia voltage reference b5 test ia analogue test c3 vreg oa reference voltage input b3 vbloom oa internal reference voltage a3 vbltw ia bitline test white reference c4 vbg oa internally generated bangap reference voltage 1.22v a4 vref2v5 oa internally generated reference voltage 2.5v digital outputs e6 fst od frame start. synchronises external image capture. f7 qck od pixel sample clock. qualifies video output for external image capture. g6,e5, g5,f5, g4,f4, g3,e4 d[7:0] od - parallel 8-wire databus. vv5301/VV6301 only, bidirectional pads always configured as outputs digital control signals e3 scl bi - serial bus clock (bidirectional, open drain) f1 sda bi - serial bus data (bidirectional, open drain) d1 qcktri id qck tristate d2 ce id - chip enable
vv5301 & VV6301 pinout and pin descriptions preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 44/49 a6 hpix id hold pixel value. e7 sin id sensor synchronisation system clocks g1 clki id oscillator input. f2 clko od oscillator output. key a analog input i d digital input oa analog output id - digital input with internal pull-up bi bidirectional id digital input with internal pull-down bi - bidirectional with internal pull-up od digital output bi bidirectional with internal pull-down odt tri-stateable digital output bga pin name type description
vv5301/VV6301 recommended reference design vv5301 & VV6301 45/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 10. vv5301/VV6301 recommended reference design
vv5301 & VV6301 package details (48 pin bga (vv5301/VV6301)) preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 46/49 11. package details (48 pin bga (vv5301/VV6301)) figure 23 : package drawing for 48pin bga with vvx301
evaluation kits (evks) vv5301 & VV6301 47/49 preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 12. evaluation kits (evks) it is highly recommended that an evaluation kit (evk) is used for initial evaluation and design-in of the vv5301/VV6301. please contact stmicroelectronics for further details.
vv5301 & VV6301 ordering details preliminary release cd5301_6301_f.fm commercial in confidence preliminary release 48/49 13. ordering details part number description vv5301b001 bga packaged, qsif monochrome sensor VV6301b001 bga packaged, qsif colour sensor stv-5301-r01 reference design board for (mono) 5301 sensor stv-6301-r01 reference design board for (colour) 6301 sensor stv-5301-e01 evaluation kit (monochrome) stv-6301-e01 evaluation kit (colour)
commercial in confidence 49/49 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved . vlsi vision l imited a company of the st microelectronics group ? cd5301_6301_f.fm ordering details vv5301 & VV6301 preliminary release preliminary release www.vvl.co.uk www.st.com asiapacific_sales@vvl.co.uk central_europe_sales@vvl.co.uk france_sales@vvl.co.uk japan_sales@vvl.co.uk nordic_sales@vvl.co.uk southern_europe_sales@vvl.co.uk uk_eire_sales@vvl.co.uk usa_sales@vvl.co.uk

▲Up To Search▲

Price & Availability of VV6301

	To Download VV6301 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .